p-channel logic level enhancement mode field effect transistor P8006EDG to-252 lead-free niko-sem 1 aug-19-2004 absolute maximum ratings (t c = 25 c unless otherwise noted) parameters/test conditions symbol limits units drain-source voltage v ds -55 v gate-source voltage v gs 20 v t c = 25 c -7 continuous drain current t c = 70 c i d -6 pulsed drain current 1 i dm -30 a t c = 25 c 28 power dissipation t c = 70 c p d 18 w operating junction & storage temperature range t j , t stg -55 to 150 lead temperature ( 1 / 16 ? from case for 10 sec.) t l 275 c thermal resistance ratings thermal resistance symbol typical maximum units junction-to-case r j c 3 c / w junction-to-ambient r ja 75 c / w 1 pulse width limited by maximum junction temperature. 2 duty cycle 1 % electrical characteristics (t c = 25 c, unless otherwise noted) limits parameter symbol test conditions min typ max unit static drain-source breakdown voltage v (br)dss v gs = 0v, i d = -250 a -55 gate threshold voltage v gs(th) v ds = v gs , i d = -250 a -1 -1.5 -2.5 v gate-body leakage i gss v ds = 0v, v gs = 20v 250 na v ds = -44v, v gs = 0v 1 zero gate voltage drain current i dss v ds = -36v, v gs = 0v, t j = 125 c 10 a on-state drain current 1 i d(on) v ds = -5v, v gs = -10v -32 a product summary v (br)dss r ds(on) i d -55v 80m ? -8a g s d 1. gate 2. drain 3. source
p-channel logic level enhancement mode field effect transistor P8006EDG to-252 lead-free niko-sem 2 aug-19-2004 v gs = -4.5v, i d = -6a 90 150 drain-source on-state resistance 1 r ds(on) v gs = -10v, i d = -7a 60 80 m ? forward transconductance 1 g fs v ds = -10v, i d = -7a 9 s dynamic input capacitance c iss 760 output capacitance c oss 90 reverse transfer capacitance c rss v gs = 0v, v ds = -30v, f = 1mhz 40 pf total gate charge 2 q g 15 gate-source charge 2 q gs 2.5 gate-drain charge 2 q gd v ds = 0.5v (br)dss , v gs = -10v, i d = -7a 3.0 nc turn-on delay time 2 t d(on) 7 14 rise time 2 t r v ds = -20v, r l = 1 ? 10 20 turn-off delay time 2 t d(off) i d ? -1a, v gs = -10v, r gs = 6 ? 19 34 fall time 2 t f 12 22 ns source-drain diode ratin gs and characteristics (t c = 25 c) continuous current i s -1.3 pulsed current 3 i sm -2.6 a forward voltage 1 v sd i f = i s , v gs = 0v -1 v reverse recovery time t rr i f = -7 a, dl f /dt = 100a / s 15.5 ns reverse recovery charge q rr 7.9 nc 1 pulse test : pulse width 300 sec, duty cycle 2 . 2 independent of operating temperature. 3 pulse width limited by maximum junction temperature. remark: the product marked with ?P8006EDG?, date code or lot # orders for parts with lead-free plating can be placed using the pxxxxxxg parts name.
p-channel logic level enhancement mode field effect transistor P8006EDG to-252 lead-free niko-sem 3 aug-19-2004 typical performance characteristics body diode forward voltage variation with source current and temperature t = 125 c -v - body diode forward voltage(v) -is - reverse drain current(a) 0.001 0 0.01 0.1 0.4 sd 0.2 0.6 25 c v = 0v 1 10 100 a gs 1.0 0.8 1.2 -55 c 1.4
p-channel logic level enhancement mode field effect transistor P8006EDG to-252 lead-free niko-sem 4 aug-19-2004
p-channel logic level enhancement mode field effect transistor P8006EDG to-252 lead-free niko-sem 5 aug-19-2004 to-252 (dpak) mechanical data mm mm dimension min. typ. max. dimension min. typ. max. a 9.35 10.4 h 0.89 2.03 b 2.2 2.4 i 6.35 6.80 c 0.45 0.6 j 5.2 5.5 d 0.89 1.5 k 0.6 1 e 0.45 0.69 l 0.5 0.9 f 0.03 0.23 m 3.96 4.57 5.18 g 5.2 6.2 n g a h j i b c m l k d e f 13 2
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